1. Field of the Invention
The present invention relates generally to a method and arrangement for rearranging an instruction sequence, and more specifically to such an arrangement and method for rearranging a sequence of instructions whose order of arrangement is subject to constraint such as in a reduced instruction set computer (RISC) architecture.
2. Description of the Prior Art
As is well known in the art, the RISC has emerged as a popular means of achieving high-performance computing. The RISC architectures take a dramatically different approach from that of systems which have been using even larger and more complex instruction sets. The RISC approach is to create a system which is simpler in architecture and faster in implementation than a complex instruction set computer (CISC) machine. That is, the RISC architecture realizes high-performance computing by reducing the burdens on a central processing unit (CPU) through reducing instructions and the resources of instructions.
However, compilers for RISC machines encounter some problems which are not experienced with conventional CISC compilers.
For example, in a RISC machine with a delayed branch, an instruction following the branch instruction will be executed irrespective of whether or not the branch is taken. Further, the executed result of a certain instruction is often not available to the instruction which immediately follows the same. In these situations, the simplest solution is simply to insert a non-operation (NOP) after each of the instructions wherein a delay is encountered. As an alternative to this simplistic solution, it has been proposed that instructions which are not effected by delays, be provided immediately after those which induce the same.
Accordingly, the RISC machine or RISC compiler has encountered the drawback that it is often difficult to arrange the instructions exactly in accordance with a job design and in the same manner as is possible with conventional type complex instruction set (CISC) machines.